1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor memory device using an SOI (Silicon (Semiconductor) On Insulator) substrate.
2. Description of the Background Art
A semiconductor memory device capable of storing data is provided as one of semiconductor devices. Generally, semiconductor memory devices are roughly classified into volatile memories including a random access memory (RAM) and non-volatile memories including a read only memory (ROM). Volatile memories are further classified into dynamic random access memories (DRAMs) and static random access memories (SRAMs). Non-volatile memories include a mask ROM, an EPROM, a flash memory, an EEPROM and a fuse ROM.
The most common memory cell in a DRAM includes an n channel MOS transistor and a capacitor formed on a p type silicon substrate. The transistor has one source/drain electrode connected to a bit line and the other source/drain electrode connected to a storage node of the capacitor. Therefore, when a word line rises, the transistor turns on, thereby applying a voltage of the bit line to the capacitor. When the word line falls, data is stored in the capacitor.
As described above, a memory cell of a DRAM requires refreshing because data is stored therein by accumulating electrical charges in a capacitor. However, since the structure of a memory cell is simple, a DRAM having a large storage capacity can be manufactured at a low cost.
However, since data is stored in the DRAM memory cell by accumulating charges in the capacitor, .alpha.-particles generated in a package, interconnection material, and the like are injected into a silicon substrate, thereby changing the amount of charges stored in the capacitor. More specifically, inversion of the logic of the stored data, the so-called soft error, is apt to occur. Especially in a trench memory cell, the soft error is more apt to occur than a stacked memory cell because its capacitor is formed in the silicon substrate.
In addition, although elements formed on the silicon substrate are electrically isolated by element isolation regions using the LOCOS (Locational Oxidation of Silicon), the field shield method or the like, a complete element isolation has been principally impossible because of the great thickness of the silicon substrate. As a result, there has been a problem that the so-called latch-up tends to occur in which normal operation is hindered by a parasitic MOS transistor attaining an on-state.
Furthermore, since the LOCOS isolation region and the field shield isolation region described above are generally thicker than the element active region, it has been difficult to form various films in these regions.
When a fuse link employed in such as a redundancy circuit of DRAMs is to be blown out with a laser, a considerable thought must be given to the arrangement or the structure of the fuse link so that the silicon substrate under the fuse link is not damaged by emission of the laser. Similarly in bonding wires to bonding pads, thought should also be given to the arrangement or the structure of pads so that the silicon substrate is not damaged by the impact of bonding.
If elements on an SOI substrate are isolated by LOCOS method or the field shield method, the difference in level between the element isolation region and the element active region is great and the subsequent step of stacking layers is difficult. Another problem remains unsolved that a crack tends to be generated in the LOCOS isolation region, the field shield isolation region, the silicon active layer, the buried oxide layer and the like during the dicing step in which the silicon wafer is cut into a plurality of chips.